startup_py32f002ax5.s 8.7 KB

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  1. ;******************************************************************************
  2. ;* @file : startup_py32f002ax5.s
  3. ;* @brief : PY32F002Axx devices vector table for MDK-ARM toolchain.
  4. ;* This module performs:
  5. ;* - Set the initial SP
  6. ;* - Set the initial PC == Reset_Handler
  7. ;* - Set the vector table entries with the exceptions ISR address
  8. ;* - Branches to __main in the C library (which eventually
  9. ;* calls main()).
  10. ;* After Reset the CortexM0+ processor is in Thread mode,
  11. ;* priority is Privileged, and the Stack is set to Main.
  12. ;******************************************************************************
  13. ;* @attention
  14. ;*
  15. ;* <h2><center>&copy; Copyright (c) 2023 Puya Semiconductor Co.
  16. ;* All rights reserved.</center></h2>
  17. ;*
  18. ;* This software component is licensed by Puya under BSD 3-Clause license,
  19. ;* the "License"; You may not use this file except in compliance with the
  20. ;* License. You may obtain a copy of the License at:
  21. ;* opensource.org/licenses/BSD-3-Clause
  22. ;*
  23. ;******************************************************************************
  24. ;* @attention
  25. ;*
  26. ;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  27. ;* All rights reserved.</center></h2>
  28. ;*
  29. ;* This software component is licensed by ST under BSD 3-Clause license,
  30. ;* the "License"; You may not use this file except in compliance with the
  31. ;* License. You may obtain a copy of the License at:
  32. ;* opensource.org/licenses/BSD-3-Clause
  33. ;*
  34. ;******************************************************************************
  35. ;* <<< Use Configuration Wizard in Context Menu >>>
  36. ; Amount of memory (in bytes) allocated for Stack
  37. ; Tailor this value to your application needs
  38. ; <h> Stack Configuration
  39. ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  40. ; </h>
  41. Stack_Size EQU 0x00000400
  42. AREA STACK, NOINIT, READWRITE, ALIGN=3
  43. Stack_Mem SPACE Stack_Size
  44. __initial_sp
  45. ; <h> Heap Configuration
  46. ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  47. ; </h>
  48. Heap_Size EQU 0x00000000
  49. AREA HEAP, NOINIT, READWRITE, ALIGN=3
  50. __heap_base
  51. Heap_Mem SPACE Heap_Size
  52. __heap_limit
  53. PRESERVE8
  54. THUMB
  55. ; Vector Table Mapped to Address 0 at Reset
  56. AREA RESET, DATA, READONLY
  57. EXPORT __Vectors
  58. EXPORT __Vectors_End
  59. EXPORT __Vectors_Size
  60. __Vectors DCD __initial_sp ; Top of Stack
  61. DCD Reset_Handler ; Reset Handler
  62. DCD NMI_Handler ; NMI Handler
  63. DCD HardFault_Handler ; Hard Fault Handler
  64. DCD 0 ; Reserved
  65. DCD 0 ; Reserved
  66. DCD 0 ; Reserved
  67. DCD 0 ; Reserved
  68. DCD 0 ; Reserved
  69. DCD 0 ; Reserved
  70. DCD 0 ; Reserved
  71. DCD SVC_Handler ; SVCall Handler
  72. DCD 0 ; Reserved
  73. DCD 0 ; Reserved
  74. DCD PendSV_Handler ; PendSV Handler
  75. DCD SysTick_Handler ; SysTick Handler
  76. ; External Interrupts
  77. DCD 0 ; 0Reserved
  78. DCD 0 ; 1Reserved
  79. DCD 0 ; 2Reserved
  80. DCD FLASH_IRQHandler ; 3FLASH
  81. DCD RCC_IRQHandler ; 4RCC
  82. DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
  83. DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
  84. DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
  85. DCD 0 ; 8Reserved
  86. DCD 0 ; 9Reserved
  87. DCD 0 ; 10Reserved
  88. DCD 0 ; 11Reserved
  89. DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
  90. DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
  91. DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
  92. DCD 0 ; 15Reserved
  93. DCD 0 ; 16Reserved
  94. DCD LPTIM1_IRQHandler ; 17LPTIM1
  95. DCD 0 ; 18Reserved
  96. DCD 0 ; 19Reserved
  97. DCD 0 ; 20Reserved
  98. DCD TIM16_IRQHandler ; 21TIM16
  99. DCD 0 ; 22Reserved
  100. DCD I2C1_IRQHandler ; 23I2C1
  101. DCD 0 ; 24Reserved
  102. DCD SPI1_IRQHandler ; 25SPI1
  103. DCD 0 ; 26Reserved
  104. DCD USART1_IRQHandler ; 27USART1
  105. DCD 0 ; 28Reserved
  106. DCD 0 ; 29Reserved
  107. DCD 0 ; 30Reserved
  108. DCD 0 ; 31Reserved
  109. __Vectors_End
  110. __Vectors_Size EQU __Vectors_End - __Vectors
  111. AREA |.text|, CODE, READONLY
  112. ; Reset Handler
  113. Reset_Handler PROC
  114. EXPORT Reset_Handler [WEAK]
  115. IMPORT SystemInit
  116. IMPORT __main
  117. LDR R0, =SystemInit
  118. BLX R0
  119. LDR R0, =__main
  120. BX R0
  121. ENDP
  122. ; Dummy Exception Handlers (infinite loops which can be modified)
  123. NMI_Handler PROC
  124. EXPORT NMI_Handler [WEAK]
  125. B .
  126. ENDP
  127. HardFault_Handler\
  128. PROC
  129. EXPORT HardFault_Handler [WEAK]
  130. B .
  131. ENDP
  132. SVC_Handler PROC
  133. EXPORT SVC_Handler [WEAK]
  134. B .
  135. ENDP
  136. PendSV_Handler PROC
  137. EXPORT PendSV_Handler [WEAK]
  138. B .
  139. ENDP
  140. SysTick_Handler PROC
  141. EXPORT SysTick_Handler [WEAK]
  142. B .
  143. ENDP
  144. Default_Handler PROC
  145. EXPORT FLASH_IRQHandler [WEAK]
  146. EXPORT RCC_IRQHandler [WEAK]
  147. EXPORT EXTI0_1_IRQHandler [WEAK]
  148. EXPORT EXTI2_3_IRQHandler [WEAK]
  149. EXPORT EXTI4_15_IRQHandler [WEAK]
  150. EXPORT ADC_COMP_IRQHandler [WEAK]
  151. EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
  152. EXPORT TIM1_CC_IRQHandler [WEAK]
  153. EXPORT LPTIM1_IRQHandler [WEAK]
  154. EXPORT TIM16_IRQHandler [WEAK]
  155. EXPORT I2C1_IRQHandler [WEAK]
  156. EXPORT SPI1_IRQHandler [WEAK]
  157. EXPORT USART1_IRQHandler [WEAK]
  158. FLASH_IRQHandler
  159. RCC_IRQHandler
  160. EXTI0_1_IRQHandler
  161. EXTI2_3_IRQHandler
  162. EXTI4_15_IRQHandler
  163. ADC_COMP_IRQHandler
  164. TIM1_BRK_UP_TRG_COM_IRQHandler
  165. TIM1_CC_IRQHandler
  166. LPTIM1_IRQHandler
  167. TIM16_IRQHandler
  168. I2C1_IRQHandler
  169. SPI1_IRQHandler
  170. USART1_IRQHandler
  171. B .
  172. ENDP
  173. ALIGN
  174. ; User Initial Stack & Heap
  175. IF :DEF:__MICROLIB
  176. EXPORT __initial_sp
  177. EXPORT __heap_base
  178. EXPORT __heap_limit
  179. ELSE
  180. IMPORT __use_two_region_memory
  181. EXPORT __user_initial_stackheap
  182. __user_initial_stackheap
  183. LDR R0, = Heap_Mem
  184. LDR R1, =(Stack_Mem + Stack_Size)
  185. LDR R2, = (Heap_Mem + Heap_Size)
  186. LDR R3, = Stack_Mem
  187. BX LR
  188. ALIGN
  189. ENDIF
  190. END