startup_py32f002bxx.s 8.7 KB

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  1. ;******************************************************************************
  2. ;* @file startup_py32f002bxx.s
  3. ;* @author MCU Application Team
  4. ;* @brief PY32F002Bxx devices vector table for MDK-ARM toolchain.
  5. ;* This module performs:
  6. ;* - Set the initial SP
  7. ;* - Set the initial PC == Reset_Handler
  8. ;* - Set the vector table entries with the exceptions ISR address
  9. ;* - Branches to __main in the C library (which eventually
  10. ;* calls main()).
  11. ;* After Reset the CortexM0+ processor is in Thread mode,
  12. ;* priority is Privileged, and the Stack is set to Main.
  13. ;******************************************************************************
  14. ;* @attention
  15. ;*
  16. ;* <h2><center>&copy; Copyright (c) 2023 Puya Semiconductor Co.
  17. ;* All rights reserved.</center></h2>
  18. ;*
  19. ;* This software component is licensed by Puya under BSD 3-Clause license,
  20. ;* the "License"; You may not use this file except in compliance with the
  21. ;* License. You may obtain a copy of the License at:
  22. ;* opensource.org/licenses/BSD-3-Clause
  23. ;*
  24. ;******************************************************************************
  25. ;* @attention
  26. ;*
  27. ;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  28. ;* All rights reserved.</center></h2>
  29. ;*
  30. ;* This software component is licensed by ST under BSD 3-Clause license,
  31. ;* the "License"; You may not use this file except in compliance with the
  32. ;* License. You may obtain a copy of the License at:
  33. ;* opensource.org/licenses/BSD-3-Clause
  34. ;*
  35. ;******************************************************************************
  36. ;* <<< Use Configuration Wizard in Context Menu >>>
  37. ; Amount of memory (in bytes) allocated for Stack
  38. ; Tailor this value to your application needs
  39. ; <h> Stack Configuration
  40. ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  41. ; </h>
  42. Stack_Size EQU 0x00000400
  43. AREA STACK, NOINIT, READWRITE, ALIGN=3
  44. Stack_Mem SPACE Stack_Size
  45. __initial_sp
  46. ; <h> Heap Configuration
  47. ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  48. ; </h>
  49. Heap_Size EQU 0x00000000
  50. AREA HEAP, NOINIT, READWRITE, ALIGN=3
  51. __heap_base
  52. Heap_Mem SPACE Heap_Size
  53. __heap_limit
  54. PRESERVE8
  55. THUMB
  56. ; Vector Table Mapped to Address 0 at Reset
  57. AREA RESET, DATA, READONLY
  58. EXPORT __Vectors
  59. EXPORT __Vectors_End
  60. EXPORT __Vectors_Size
  61. __Vectors DCD __initial_sp ; Top of Stack
  62. DCD Reset_Handler ; Reset Handler
  63. DCD NMI_Handler ; NMI Handler
  64. DCD HardFault_Handler ; Hard Fault Handler
  65. DCD 0 ; Reserved
  66. DCD 0 ; Reserved
  67. DCD 0 ; Reserved
  68. DCD 0 ; Reserved
  69. DCD 0 ; Reserved
  70. DCD 0 ; Reserved
  71. DCD 0 ; Reserved
  72. DCD SVC_Handler ; SVCall Handler
  73. DCD 0 ; Reserved
  74. DCD 0 ; Reserved
  75. DCD PendSV_Handler ; PendSV Handler
  76. DCD SysTick_Handler ; SysTick Handler
  77. ; External Interrupts
  78. DCD 0 ; 0Reserved
  79. DCD 0 ; 1Reserved
  80. DCD 0 ; 2Reserved
  81. DCD FLASH_IRQHandler ; 3FLASH
  82. DCD RCC_IRQHandler ; 4RCC
  83. DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
  84. DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
  85. DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
  86. DCD 0 ; 8Reserved
  87. DCD 0 ; 9Reserved
  88. DCD 0 ; 10Reserved
  89. DCD 0 ; 11Reserved
  90. DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
  91. DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
  92. DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
  93. DCD 0 ; 15Reserved
  94. DCD 0 ; 16Reserved
  95. DCD LPTIM1_IRQHandler ; 17LPTIM1
  96. DCD 0 ; 18Reserved
  97. DCD TIM14_IRQHandler ; 19TIM14
  98. DCD 0 ; 20Reserved
  99. DCD 0 ; 21Reserved
  100. DCD 0 ; 22Reserved
  101. DCD I2C1_IRQHandler ; 23I2C1
  102. DCD 0 ; 24Reserved
  103. DCD SPI1_IRQHandler ; 25SPI1
  104. DCD 0 ; 26Reserved
  105. DCD USART1_IRQHandler ; 27USART1
  106. DCD 0 ; 28Reserved
  107. DCD 0 ; 29Reserved
  108. DCD 0 ; 30Reserved
  109. DCD 0 ; 31Reserved
  110. __Vectors_End
  111. __Vectors_Size EQU __Vectors_End - __Vectors
  112. AREA |.text|, CODE, READONLY
  113. ; Reset Handler
  114. Reset_Handler PROC
  115. EXPORT Reset_Handler [WEAK]
  116. IMPORT SystemInit
  117. IMPORT __main
  118. LDR R0, =SystemInit
  119. BLX R0
  120. LDR R0, =__main
  121. BX R0
  122. ENDP
  123. ; Dummy Exception Handlers (infinite loops which can be modified)
  124. NMI_Handler PROC
  125. EXPORT NMI_Handler [WEAK]
  126. B .
  127. ENDP
  128. HardFault_Handler\
  129. PROC
  130. EXPORT HardFault_Handler [WEAK]
  131. B .
  132. ENDP
  133. SVC_Handler PROC
  134. EXPORT SVC_Handler [WEAK]
  135. B .
  136. ENDP
  137. PendSV_Handler PROC
  138. EXPORT PendSV_Handler [WEAK]
  139. B .
  140. ENDP
  141. SysTick_Handler PROC
  142. EXPORT SysTick_Handler [WEAK]
  143. B .
  144. ENDP
  145. Default_Handler PROC
  146. EXPORT FLASH_IRQHandler [WEAK]
  147. EXPORT RCC_IRQHandler [WEAK]
  148. EXPORT EXTI0_1_IRQHandler [WEAK]
  149. EXPORT EXTI2_3_IRQHandler [WEAK]
  150. EXPORT EXTI4_15_IRQHandler [WEAK]
  151. EXPORT ADC_COMP_IRQHandler [WEAK]
  152. EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
  153. EXPORT TIM1_CC_IRQHandler [WEAK]
  154. EXPORT LPTIM1_IRQHandler [WEAK]
  155. EXPORT TIM14_IRQHandler [WEAK]
  156. EXPORT I2C1_IRQHandler [WEAK]
  157. EXPORT SPI1_IRQHandler [WEAK]
  158. EXPORT USART1_IRQHandler [WEAK]
  159. FLASH_IRQHandler
  160. RCC_IRQHandler
  161. EXTI0_1_IRQHandler
  162. EXTI2_3_IRQHandler
  163. EXTI4_15_IRQHandler
  164. ADC_COMP_IRQHandler
  165. TIM1_BRK_UP_TRG_COM_IRQHandler
  166. TIM1_CC_IRQHandler
  167. LPTIM1_IRQHandler
  168. TIM14_IRQHandler
  169. I2C1_IRQHandler
  170. SPI1_IRQHandler
  171. USART1_IRQHandler
  172. B .
  173. ENDP
  174. ALIGN
  175. ; User Initial Stack & Heap
  176. IF :DEF:__MICROLIB
  177. EXPORT __initial_sp
  178. EXPORT __heap_base
  179. EXPORT __heap_limit
  180. ELSE
  181. IMPORT __use_two_region_memory
  182. EXPORT __user_initial_stackheap
  183. __user_initial_stackheap
  184. LDR R0, = Heap_Mem
  185. LDR R1, =(Stack_Mem + Stack_Size)
  186. LDR R2, = (Heap_Mem + Heap_Size)
  187. LDR R3, = Stack_Mem
  188. BX LR
  189. ALIGN
  190. ENDIF
  191. END
  192. ;************************ (C) COPYRIGHT Puya *****END OF FILE*******************